1. Field of the Invention
This invention relates to semiconductor devices and more particularly to a static random access memory semiconductor devices.
2. Description of Related Art
In VLSI semiconductor circuits memories are formed of semiconductor devices, which store data by means of electric charges. Different types of such memories include Static Random Access Memories (SRAM's), Dynamic Random Access Memories (DRAM's), Read Only Memories (ROMs), etc. These semiconductor memory devices can be packed in very large numbers of memory cells with a large storage capacity in a space with very low volume and can be manufactured at a low cost. Among these memories, the static type semiconductor memory has been widely used as a random access memory (RAM), because it can retain stored data without periodically being refreshed during operation.
The static random access memory (SRAM) can be implemented by a large number of bistable flip-flop circuits each of which stores one bit of information. The CMOS flip-flop circuit is composed of a pair of N-channel MOS field effect transistors and a pair of P-channel MOS Field effect transistors used as a memory cell because of the very low power consumption of the CMOS flip-flop circuit. However, the CMOS flip-flop circuit generally requires a relatively large surface area on a semiconductor substrate, so in the past, there has been a limitation to the capacity of an SRAM by employing the CMOS flip-flop.
Several years ago, a design was adopted in which the cell includes a partial substitution of thin film transistors (TFTs) for the buried FET devices of a pair of P-channel MOS transistors of the CMOS flip-flop circuit in a Silicon-On-Insulator (SOI) structure. According to the TFT or SOI technique, the N channel MOS transistors are formed at a surface of a semiconductor substrate and the P-channel MOS transistors have been fabricated by a polycrystalline silicon layer or a monocrystalline silicon layer which is formed on the surface of the semiconductor substrate over an insulating layer. According to this technique, the P-channel transistors can overlap a part of the N-channel MOS transistors, and therefore the space required by each cell of an SRAM is reduced.
A problem with the above approach is that typical polysilicon TFTs suffer from a high negative threshold voltage.